In a significant leap for microelectronics, researchers at The Hong Kong Polytechnic University (PolyU) have engineered a novel tunnelling field-effect transistor (TFET) that overcomes the physical constraints limiting conventional semiconductor technology. This breakthrough, published in the journal Science, could be instrumental in developing energy-efficient computing and next-generation AI chips, addressing a critical bottleneck in the industry.
Conventional transistors rely on thermionic emission, which requires a minimum gating voltage of 60 millivolts (mV) at room temperature. This limit, known as the 'Boltzmann limit', makes subthreshold swing (SS) values below 60 mV per decade physically impossible, restricting improvements in energy efficiency and performance. The PolyU-led research team has circumvented this barrier by adopting quantum tunnelling, a mechanism that allows charge carriers to pass through an energy barrier rather than over it.
Professor Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, who led the research, explained, "By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications."
The team created an ultra-thin heterostructure of alternating layers of 2D bismuth and indium selenide using pulsed laser deposition. By precisely controlling the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, allowing efficient quantum tunnelling of charge carriers into indium selenide. This design enabled the TFET to achieve SS values well below the 60 mV per decade limit while operating at room temperature on silicon substrates.
The device required a gate-voltage range of only 160 mV, compared to the 800 mV typically needed, marking a substantial reduction in power consumption. Moreover, it delivered a high output current alongside an exceptionally high ON/OFF current ratio, a challenge that has previously hindered experimental TFETs. This combination allows the transistor to drive multiple downstream logic gates and diminish circuit delay, making it viable for practical integrated circuits.
The research was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings hold profound implications for the semiconductor industry, which is grappling with the limits of Moore's law and the escalating energy demands of AI and data centres. By enabling ultra-low-power transistors, this breakthrough could lead to more sustainable, high-performance computing devices, from smartphones to supercomputers, and accelerate the development of advanced AI hardware.
As the industry seeks alternatives to traditional silicon-based technology, this TFET represents a promising path forward. The ability to operate below the Boltzmann limit at room temperature and on standard silicon substrates suggests that integration with existing manufacturing processes may be feasible, potentially accelerating its adoption. The next steps for the research team include scaling the technology and addressing manufacturing challenges, but the potential impact on the global microelectronics landscape is undeniable.
